ARM Assembly Cheat Sheet

Instructions#

• Arithmetic

  Operation	Syntax	Semantic	Flags
  Addition	add{s} {Rd,} Rn, Rm {, shift}	Rd(n) := Rn + Rmshifted	NZCV
  	adc{s} {Rd,} Rn, Rm {, shift}	Rd(n) := Rn + Rmshifted + C	NZCV
  	add{s} {Rd,} Rn, #const	Rd(n) := Rn + const	NZCV
  	adc{s} {Rd,} Rn, #const	Rd(n) := Rn + const + C	NZCV
  	qadd {Rd,} Rn, Rm	Rd(n) := saturated(Rn + Rm)	Q
  Subtraction	sub{s} {Rd,} Rn, Rm {, shift}	Rd(n) := Rn − Rmshifted	NZCV
  	sbc{s} {Rd,} Rn, Rm {, shift}	Rd(n) := Rn − Rmshifted + C	NZCV
  	rsb{s} {Rd,} Rn, Rm {, shift}	Rd(n) := Rmshifted − Rn	NZCV
  	sub{s} {Rd,} Rn, #const	Rd(n) := Rn − const	NZCV
  	sbc{s} {Rd,} Rn, #const	Rd(n) := Rn − const + C	NZCV
  	rsb{s} {Rd,} Rn, #const	Rd(n) := const − Rn	NZCV
  	qsub{s} {Rd,} Rn, Rm	Rd(n) := saturated(Rn − Rm)	Q
  Multiplication	mul {Rd,} Rn, Rm	Rd(n) := Rn × Rm	-
  	mla Rd, Rn, Rm, Ra	Rd := Ra + (Rn × Rm)	-
  	mls Rd, Rn, Rm, Ra	Rd := Ra - (Rn × Rm)	-
  	umull RdLo, RdHi, Rn, Rm	RdHi:RdLo := (uint64) Rn × Rm	-
  	umlal RdLo, RdHi, Rn, Rm	RdHi:RdLo := (uint64) RdHi:RdLo + (Rn × Rm)	-
  	smull RdLo, RdHi, Rn, Rm	RdHi:RdLo := (int64) Rn × Rm	-
  	smlal RdLo, RdHi, Rn, Rm	RdHi:RdLo := (int64) RdHi:RdLo + (Rn × Rm)	-
  Division	udiv Rd, Rn, Rm	Rd := (uint32) Rn ÷ Rm (rounded to 0)	-
  	sdiv Rd, Rn, Rm	Rd := (int32) Rn ÷ Rm (rounded to 0)	-

• Logic & Tests

  Operation	Syntax	Semantic	Flags
  Logic	and{s} {Rd,} Rn, Rm {, shift}	Rd(n) := Rn ∧ Rmshifted	NZCV
  	bic{s} {Rd,} Rn, Rm {, shift}	Rd(n) := Rn ∧ ¬Rmshifted	NZCV
  	orr{s} {Rd,} Rn, Rm {, shift}	Rd(n) := Rn ∨ Rmshifted	NZCV
  	orn{s} {Rd,} Rn, Rm {, shift}	Rd(n) := Rn ∨ ¬Rmshifted	NZCV
  	eor{s} {Rd,} Rn, Rm {, shift}	Rd(n) := Rn ⊕ Rmshifted	NZCV
  	and{s} {Rd,} Rn, #const	Rd(n) := Rn ∧ const	NZCV
  	bic{s} {Rd,} Rn, #const	Rd(n) := Rn ∧ ¬const	NZCV
  	orr{s} {Rd,} Rn, #const	Rd(n) := Rn ∨ const	NZCV
  	orn{s} {Rd,} Rn, #const	Rd(n) := Rn ∨ ¬const	NZCV
  	eor{s} {Rd,} Rn, #const	Rd(n) := Rn ⊕ const	NZCV
  Test	cmp Rn, Rm {, shift}	Rn − Rmshifted	NZCV
  	cmn Rn, Rm {, shift}	Rn + Rmshifted	NZCV
  	tst Rn, Rm {, shift}	Rn ∧ Rmshifted	NZCV
  	teq Rn, Rm {, shift}	Rn ⊕ Rmshifted	NZCV
  	cmp Rn, #const	Rn − const	NZCV
  	cmn Rn, #const	Rn + const	NZCV
  	tst Rn, #const	Rn ∧ const	NZCV
  	teq Rn, #const	Rn ⊕ const	NZCV

• Moves & Shifts

  Operation	Syntax	Semantic	Flags
  Move	mov{s} Rd, Rm	Rd := Rm	NZ
  	mov{s} Rd, #const	Rd := const	NZC
  Shift/Rotate	lsl{s} Rd, Rm, Rs	Rd := Rm << Rs	NZC
  	lsr{s} Rd, Rm, Rs	Rd := (uint32) Rm >> Rs	NZC
  	asr{s} Rd, Rm, Rs	Rd := (int32) Rm >> Rs	NZC
  	ror{s} Rd, Rm, Rs	Rd := Rm << (32 − Rs) ∨ Rm >> Rs	NZC
  	lsl{s} Rd, Rm, #const	Rd := Rm << const	NZC
  	lsr{s} Rd, Rm, #const	Rd := (uint32) Rm >> const	NZC
  	asr{s} Rd, Rm, #const	Rd := (int32) Rm >> const	NZC
  	ror{s} Rd, Rm, #const	Rd := Rm << (32 - const) ∨ Rm >> const	NZC
  	rrx{s} Rd, Rm	Rd := C << 31 ∨ Rm >> 1	NZC

  For the difference between ASR and LSR see the shifts with the same names.
• Loads & Stores

  Operation	Syntax	Semantic	Flags
  Offset	ldr Rd, [Rb {, #const}]	Rd := [Rb + const]	-
  	str Rs, [Rb {, #const}]	[Rb + const] := Rs	-
  Pre-offset	ldr Rd, [Rb {, #const}]!	Rb += const; Rd := [Rb]	-
  	str Rs, [Rb {, #const}]!	Rb += const; [Rb] := Rs	-
  Post-offset	ldr Rd, [Rb], #const	Rd := [Rb]; Rb += const	-
  	str Rs, [Rb], #const	[Rb] := Rs; Rb += const	-
  Indexed	ldr Rd, [Rb, Ri {, LSL n}]	Rd := [Rb + (Ri << n)]	-
  	str Rs, [Rb, Ri {, LSL n}]	[Rb + (Ri << n)] := Rs	-
  Literal	ldr Rd, label	Rd := [label]	-
  	ldr Rd, [PC, #offset]	Rd := [PC + offset]	-
  Positive stack	stmia Rs!, registers	for Ri in registers do [Rs] := Ri; Rs += 4	-
  	ldmdb Rs!, registers	for Ri in rev(registers) do Rs -= 4; Ri := [Rs]	-
  Negative stack	stmdb Rs!, registers	for Ri in rev(registers) do Rs -= 4; [Rs] := Ri	-
  	ldmia Rs!, registers	for Ri in registers do Ri := [Rs]; Rs += 4	-

  Note: most of the ldr/str memory instructions can have h or b appended to them to change to halfword (16 bit) / byte (8 bit) operations respectively.
  Eg: ldrh r0, [r1] or strb r2, [r3]

• Branches

  Operation	Syntax	Semantic	Flags
  General	b<c> label	if c then PC := label	-
  	bl label	LR := PCnext; PC := label	-
  	bx Rm	PC := Rm	-
  	blx Rm	LR := PCnext; PC := Rm	-
  Test & branch	cbz Rn, label	if Rn = 0 then PC := label	-
  	cbnz Rn, label	if Rn ≠ 0 then PC := label	-
  Table based	tbb [Rn, Rm]	PC += (byte) [PC + Rm]	-
  	tbh [Rn, Rm {, LSL 1}]	PC += (hword) [PC + Rm << shift]	-

  <c> denotes a condition suffix. For example, use beq to branch only when the zero flag is set.
• Synchronisation

  Syntax	Semantic	Flags
  ldrex Rd, [Rn {, #const}]	Rd := [Rn + const]; EX=True	-
  strex Rt, Rs, [Rn {, #const}]	if EX then [Rn + const] := Rs; Rd := 0 else Rd := 1	-

  The synchronisation instructions work with a special "exclusive monitor" (denoted EX in the table) that tracks the "exclusive state" of the CPU.

  • Every LDREX instruction will succeed and set the exclusive state to true.
  • An STREX instruction will check the exclusive state, and if true, will execute the store, write 0 to Rd, and set the state to false. If the state was already false, the store is not executed and Rd is set to 1. This entire sequence is done atomically.
  • A context switch (such as an interrupt) will set the exclusive state to false.

  The end effect is that only the first STREX performed after the latest LDREX with no context switches in between will execute its store.

• Instructions with an optional s suffix will only change the flags if this suffix is added.
• Optional constants and shifts default to 0 / no shift.
• Square brackets such as in [Rd] denote the memory stored at the given address, in this case the address held in Rd.

Shifts#

Flags#

Conditions#

Width#

The width is an optional suffix on the instruction name (after any condition).