This page provides a more verbose description of each instruction and what it does, which is more useful when it actually comes to writing assembly, rather than implementing the CPU in hardware. There’s nothing in here that isn’t already covered in the ISA Document as far as building the CPU is concerned.

Definitions

• {x} Denotes that the given parameter x is optional and can be omitted. For example, add{z} indicates that both add and addz are valid instructions.

• [x] Denotes the data stored in memory at address x. For example, [r1] refers to the contents in memory, located at the address stored in r1.

• <x> Denotes the binary encoding for x. For an immediate value, it is the binary representation of the number of the appropraite length. For a reigster, it is the register code. For example, <3> would represent 0000 0011 (assuming an 8-bit immediate) and <r4> would represent 100.

Hardware Instructions

ADD

Syntax	Meaning	Machine Code
add{z} {rd},ra,rb	rd := ra+rb	1000 z<rd> 0<ra> 0<rb>

Description:

The ADD instruction adds the value of ra to a second operand rb and stores the result in rd.

If the destination register rd is unspecified, it is assumed to be ra.

Flags:

Z	Set if the result of this instruction was zero.
N	Set if the result of this instruction was negative.
C	Set if the result of this instruction generated a carry (an unsigned overflow).
V	Set if the result of this instruction generated an overflow.

Example:

movl r3, 10     ; r3 := 10
movl r2, 20     ; r2 := 20
add r1, r2, r3  ; r1 := r2 + r3 = 30

AND

Syntax	Meaning	Machine Code
and{z} {rd},ra,rb	rd := ra&rb	1010 z<rd> 0<ra> 0<rb>

Description:

The AND instruction computes the bitwise AND of ra and rb and stores the result in rd.

If the destination register rd is unspecified, it is assumed to be ra.

Flags:

Z	Set if the result of this instruction was zero.
N	Set if the result of this instruction was negative.
C	Set to zero.
V	Set to zero.

Example:

movl r1, 0b1100  ; r1 := 0b1100 = 12
movl r2, 0b1010  ; r2 := 0b1010 = 10
and r3, r1, r2   ; r3 := 0b1100 & 0b1010 = 0b1000 = 8

MOVL

Syntax	Meaning	Machine Code
movl{z} rd,imm8	rd := #imm8	0000 z<rd> <imm8>

Description:

The MOVL instruction loads a 8-bit immediate, extends it with zeros, and writes it to register rd. The low byte of rd contains imm8, and the high byte of rd contains zero after executing this instruction.

Flags:

Z	Unchanged.
N	Unchanged.
C	Unchanged.
V	Unchanged.

Example:

movl r1, 6  ; r1 = 6

LDR

Syntax	Meaning	Machine Code
ldr{z} rd,[ra]	rd := [ra]	0101 z<rd> 0<ra> 0000

Description:

The LDR loads a word from memory specified by the memory address in ra as appropriate, and stores the result into rd.

Flags:

Z	Unchanged.
N	Unchanged.
C	Unchanged.
V	Unchanged.

Example:

               ; assume memory slot 0x10 contains value 13
movl r1, 1     ; r1 = 1
movl r2, 0x10  ; r2 = 0x10
ldr r3, [r2]   ; r3 = memory[0x10] = 13
add r3, r1     ; r3 = 14
str r3, [r2]   ; memory slot 0x10 now contains 14

ORR

Syntax	Meaning	Machine Code
orr{z} {rd},ra,rb	rd := ra|rb	1011 z<rd> 0<ra> 0<rb>

Description:

The ORR instruction computes the bitwise ORR of ra and rb, and stores the result in rd.

If the destination register rd is unspecified, it is assumed to be ra.

Flags:

Z	Set if the result of this instruction was zero.
N	Set if the result of this instruction was negative.
C	Set to zero.
V	Set to zero.

Example:

movl r1, 0b1100  ; r1 = 0b1100 = 12
movl r2, 0b1010  ; r2 = 0b1010 = 10
orr r3, r1, r2   ; r3 = 0b1110 = 14

SETH

Syntax	Meaning	Machine Code
seth{z} rd, <#imm8>	See below	0001 z<rd> <imm8>

Description:

The SETH instruction moves a constant into the high byte of the destination register rd, leaving the low byte of rd unchanged. Formally, rd = (#imm8 << 8) | (rd & 0xff).

Contrast with MOVL, which moves an 8-bit immediate into the low byte of a register, and zeros out the high byte.

Flags:

Z	Unchanged.
N	Unchanged.
C	Unchanged.
V	Unchanged.

Example:

               ; want r1 to contain 0x1234
movl r1, 0x34  ; r1 = 0x0034
seth r1, 0x12  ; r1 = 0x1234
movl r1, 0x12  ; r1 = 0x0012

STR

Syntax	Meaning	Machine Code
str{z} rd,[ra]	mem[ra] := rd	0100 z<rd> 0<ra> 0000

Description:

The STR stores a word from memory contained in rd to the memory address ra

Flags:

Z	Unchanged.
N	Unchanged.
C	Unchanged.
V	Unchanged.

Example:

               ; assume memory slot 0x10 contains value 13
movl r1, 1     ; r1 = 1
movl r2, 0x10  ; r2 = 0x10
ldr r3, [r2]   ; r3 = memory[0x10] = 13
add r3, r1     ; r3 = 14
str r3, [r2]   ; memory slot 0x10 now contains 14

SUB

Syntax	Meaning	Machine Code
sub{z} {rd}, ra, rb	rd := ra + rb	1000 z<rd> 0<ra> 0<rb>

Description:

The SUB instruction subtracts the value in rb from the value in ra and stores the result in rd.

If the destination register rd is unspecified, it is assumed to be ra.

Flags:

Z	Set if the result of this instruction was zero.
N	Set if the result of this instruction was negative.
C	Set if the result of this instruction generated a carry (an unsigned overflow).
V	Set if the result of this instruction generated an overflow.

Example:

movl r3, 10     ; r3 = 10
movl r2, 20     ; r2 = 20
sub r1, r3, r2  ; r1 = -10

Pseudo-Instructions

These instructions are special cases of instruction that already exist in the ISA, but make writing assembly a bit easier. By implementing the base ISA instructions, the pseudo-instructions are obtained for free.

Syntax	Meaning	Machine Code
mov{z} rd, ra	rd := ra	1000 z<rd> 0<ra> 0000
jpr{z} ra	pc := ra	1000 z111 0<ra> 0000
cmp{z} ra, rb	ra - rb	1001 z000 0<ra> 0<rb>
nop	Do nothing	0000 0000 0000 0000
jpm{z} [ra]	pc := [ra]	0101 z111 0<ra> 0000
jp{z} imm8	pc := imm8	0000 z111 <imm8>
jp{z} <label>	pc := <label>	Up to the assembler

The compare instruction cmp is useful for comparing the values between two registers. It is synthesised as a subtraction with rz as the destination register (cmp{z} ra, rb is equivalent to sub{z} rz, ra, rb), which means the result of the subtraction is discarded, but the flags are still set.

cmp r1, r2   ; if r1 == r2:
movlz r3, 1  ;     r3 = 1